Semiconductor device and method for fabricating the same

ABSTRACT

A semiconductor device and a method for fabricating the same are provided to enable a bit line to be formed easily, increase a bit line process margin and reduce capacitance between the adjacent bit lines. The semiconductor device comprises: a first pillar and a second pillar each extended vertically from a semiconductor substrate and including a vertical channel region; a first bit line located in the lower portion of the vertical channel region inside the first pillar and the second pillar; and an interlayer insulating film located between the first pillar and the second pillar that include the first bit line.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to Korean patent application No.10-2011-0112418 filed on Oct. 31, 2011, which is incorporated byreference in its entirety.

BACKGROUND OF THE INVENTION

1. Technical Field

The inventive concept relates generally to a semiconductor device and amethod for fabricating the same, and more particularly to asemiconductor device that comprises a vertical channel transistor and amethod for fabricating the same.

2. Related Art

In general, a semiconductor, as a material which belongs in anintermediate range between a conductor and a nonconductor by materialclassification depending on electric conductivity, has similarproperties as a pure nonconductor, but its electric conductivity may beincreased by the addition of impurities or by other manipulations. Asemiconductor material is used for generating a semiconductor devicesuch as a transistor by adding impurities and connecting devicecomponents. A semiconductor apparatus refers to an apparatusmanufactured using such a semiconductor device with various functions. Arepresentative example of a semiconductor apparatus is a semiconductormemory apparatus.

A semiconductor memory apparatus comprises a plurality of unit cellsincluding a capacitor and a transistor. The capacitor is used to storedata and the transistor is used to transfer data between the capacitorand a bit line in response to a control signal (a word line) using asemiconductor property in which electric conductivity changes accordingto conditions. The transistor has three parts including a gate, asource, and a drain. Electric charges move between the source and drainaccording to the control signal input to the gate. The electric chargesmove between the source and drain through a channel region usingsemiconductor properties.

When a conventional transistor is fabricated on a semiconductorsubstrate, the gate is formed over the semiconductor substrate and thenthe source and drain are formed by implanting impurities into thesemiconductor substrate. In this case, a space between the source andthe drain below the gate is a channel region of the transistor. Such atransistor having the vertical channel region occupies a given area ofthe semiconductor substrate. In a complicated semiconductor memoryapparatus, it is difficult to reduce the whole area by a plurality oftransistors included in the semiconductor memory apparatus.

If the whole area of the semiconductor memory apparatus is reduced, thenumber of semiconductor memory apparatuses that can be produced perwafer may be increased to improve productivity. In order to reduce thewhole area of the semiconductor memory apparatus, various methods havebeen suggested. One of these methods uses a vertical transistor having avertical channel region instead of a conventional horizontal transistorhaving a horizontal channel region.

In the vertical transistor, a source and a drain are formed in the upperand the lower regions of pillars extended vertically, and a channel isformed between the source and the drain in up-and-down directions(vertically) along the pillars. The advantage of the vertical transistoris to manufacture one semiconductor cell in a narrower area than that ofthe horizontal transistor.

BRIEF SUMMARY OF THE INVENTION

Various embodiments of the invention are directed to provide asemiconductor device and a method for fabricating the same thatcomprises forming a bit line in pillars to increase a bit line processmargin and reduce capacitance between the adjacent bit lines.

According to one aspect of an exemplary embodiment, a semiconductordevice comprises: a first pillar and a second pillar each extendedvertically from a semiconductor substrate and each including a verticalchannel region; a first bit line located in the lower portion of thevertical channel region inside the first pillar and the second pillar;and an interlayer insulating film located between the first pillar andthe second pillar that include the first bit line.

The first bit line includes a metal silicide and the metal silicideincludes a cobalt silicide (CoSi₂).

The first bit line is disposed at both sides of the first pillar and thesecond pillar.

The semiconductor device further comprises a second bit line located ata sidewall of the first and second pillars in contact with the first bitline.

The second bit line includes a titanium nitride film (TiN), a tungsten(W) and a tungsten nitride film (WN) or has a stacked structureincluding at least two or more selected from a titanium nitride film(TiN), a tungsten (W) and a tungsten nitride film (WN).

The second bit line is disposed at both sides of the first pillar andthe second pillar.

The semiconductor device further comprises: upper junction regionslocated in the upper portion of the vertical channel region in the firstpillar and the second pillar; and a lower junction region located in thelower of the vertical channel region in the first pillar and the secondpillar.

The first bit line is located inside the lower junction region.

The semiconductor device further comprises a wall oxide layer located onthe surface of the first pillar and the second pillar. The wall oxidelayer is located in the vertical channel region of the first pillar andthe second pillar and the upper junction region.

The semiconductor device further comprises a spacer located on the leftand right side surfaces of the first pillar and the second pillar. Thespacer includes a nitride film.

The upper junction region and the lower junction region are an N-typeand the vertical channel region is a P-type or the upper junction regionand the lower junction region are a P-type and the vertical channelregion is an N-type.

The semiconductor device further comprises a nitride film located in theupper portion of the first pillar and the second pillar.

The interlayer insulating film includes: a first interlayer insulatingfilm; and a second interlayer insulating film located in the upperportion of the first interlayer insulating film.

The first pillar and the second pillar include a line pattern.

The semiconductor device further comprises a gate located in a regioncorresponding to the vertical channel region and extended in contactwith the vertical channel region.

The semiconductor device further comprises a capacitor located in theupper portion of the first pillar and the second pillar and connected tothe upper junction region.

According to one aspect of an exemplary embodiment, a method forfabricating a semiconductor device comprises: forming a first pillar anda second pillar over a semiconductor substrate; forming a first bit lineinside the first pillar and the second pillar; and forming an interlayerinsulating film between the first pillar and the second pillar thatinclude the first bit line.

The forming-a-first-pillar-and-a-second-pillar includes: forming apillar hard mask over the semiconductor substrate; and etching thesemiconductor substrate with the pillar hard mask as a mask.

The forming-a-first-pillar-and-a-second-pillar includes growing asilicon epitaxially over the semiconductor substrate.

After forming the first pillar and the second pillar, the method furthercomprises performing an oxidation process on the surface of the firstpillar and the second pillar to form a wall oxide layer.

Before forming the first bit line, the method further comprises forminga lower junction region in the lower of the first pillar and the secondpillar.

The forming-a-lower-junction-region includes performing anion-implanting process or a plasma doping process with phosphorus (Ph)or arsenic (As).

The forming-a-lower-junction-region includes: removing the wall oxidelayer disposed over the semiconductor substrate; and etching thesemiconductor substrate with a given depth.

The forming-a-first-bit-line includes: forming a first conductive layerover the whole surface of the first pillar and the second pillar;removing the first conductive layer disposed over the semiconductorsubstrate; and performing a rapid thermal annealing process.

The rapid thermal annealing process includes reacting a metal materialof the first conductive layer with a silicon of the first pillar and thesecond pillar.

The removing-the-first-conductive-layer includes etching thesemiconductor substrate with a given depth.

The first conductive layer includes a cobalt (Co).

After removing the first conductive layer disposed over thesemiconductor substrate, the method further comprises performing a slantetch process on the first pillar and the second pillar to etch the firstconductive layer formed on one side surface of the first pillar and thesecond pillar.

After forming the first bit line, the method further comprises forming asecond bit line on the side surface of the first pillar and the secondpillar in contact with the first bit line.

The forming-a-second-bit-line includes: forming a second conductivelayer over the whole surface of the first pillar and the second pillarwhere the first bit line is formed; removing the second conductive layerdisposed over the semiconductor substrate; forming a first interlayerinsulating film with a given height between the first pillar and thesecond pillar; and removing the second conductive layer disposed overthe first interlayer insulating film.

The forming-a-first-interlayer-insulating-film-with-a-given-heightincludes: planarizing the first interlayer insulating film disposed overthe whole surface of the first pillar and the second pillar; andperforming an etch-back process on the first interlayer insulating film.

The surface of the first interlayer insulating film has the same orhigher height than that of the upper end of the first bit line.

After forming the first bit line, the method further comprises forming aspacer including a nitride film at the sidewall of the first pillar andthe second pillar.

The method further comprises: performing a channel ion-implantingprocess on the first pillar and the second pillar to form a verticalchannel region; and performing an upper junction region ion-implantingprocess on the first pillar and the second pillar to form upper junctionregions.

The method further comprises forming a gate in contact with the verticalchannel region.

The method further comprises forming a capacitor in the upper portion ofthe first pillar and the second pillar.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and other advantages of thesubject matter of the present disclosure will be more clearly understoodfrom the following detailed description taken in conjunction with theaccompanying drawings, in which:

FIGS. 1-12 are cross-sectional diagrams illustrating a method forfabricating a semiconductor device according to an embodiment of thepresent invention.

DESCRIPTION OF EMBODIMENTS

Exemplary embodiments of the present invention will be described indetail with reference to the attached drawings.

FIG. 12 is a cross-sectional diagram illustrating a semiconductor deviceaccording to an embodiment of the present invention.

Referring to FIG. 12, pillars 12 and 14 extend in a vertical directionfrom a semiconductor substrate 10. The two pillars 12 and 14, which areadjacent to each other, are designated as a first pillar 12 and a secondpillar 14, respectively. Upper junction regions 12 a and 14 a are formedin the upper portion of the pillars 12 and 14, vertical channel regions12 b and 14 b are formed in the middle portion of the pillars 12 and 14,and a lower junction region 15 is formed in the lower portion of thepillars 12 and 14. Thus, a channel of the transistor is formed along thevertical channel region 12 b located between the upper junction region12 a and the lower junction region 15.

The lower junction region 15 may be formed as an N-type region or aP-type region. When the lower junction region 15 is formed as a N-typeregion, as shown in FIG. 12, the upper junction regions 12 a and 14 aare also formed as N-type regions and the vertical channel regions 12 band 14 b are formed as P-type regions. On the other hand, when the lowerjunction region 15 is formed as a P-type, the upper junction regions 12a and 14 a are formed as P-type regions and the vertical channel regions12 b and 14 b are formed as N-type regions.

A first bit line 22 is disposed in a lower portion of the verticalchannel region 12 b or 14 b of the pillar 12 or 14, preferably, insidethe lower junction region 15. The first bit line 22 is not formedbetween the adjacent pillars 12 and 14, but is formed inside either oneof or both of the two pillars 12 and 14. The first bit line 22 includesmetal silicide, which may include cobalt silicide (CoSi₂). It isdesirable to form the first bit line 22 at left and right sidewalls ofthe pillars 12 or 14 to reduce bit line resistance, but the first bitline 22 may be formed at only one sidewall of the pillar 12 or 14.

Outside the first bit line 22 of the pillars 12 and 14, a second bitline 26 may be formed to be in contact with the first bit line 22. Thesecond bit line 26 includes metal material, which may include a titaniumnitride film (TiN), a tungsten (W) film, a tungsten nitride film (WN) orhave a stacked structure thereof (e.g., a stacked structure including atungsten nitride film and a tungsten). It is desirable to form thesecond bit line 26 on the left and right sidewalls of the pillar 12 or14 to reduce bit line resistance, but the second bit line 26 may beformed at only one sidewall of the pillar 12 or 14.

In the pillar 12 or 14, a wall oxide layer 18 is formed on the left andthe right sidewall of the upper junction regions 12 a and 14 a and thevertical channel regions 12 b and 14 b, but not on the lower junctionregion 15. The wall oxide layer 18, which may have the same structure asthat of a gate insulating film, is formed to protect the surface of thepillars 12 and 14 including silicon material, and may be obtained byperforming a Chemical Vapor Deposition (CVD) process on High-K materialssuch as SiO, ONO, HfO₂x, ZrO or PZT materials or by heating thesemiconductor substrate in a furnace. Also, the wall oxide film 18 maybe obtained by depositing High-K materials such as Zr or Hf on thesurface of the pillars 12 and 14 by an Atomic Layer Deposition (ALD)process to be subject to natural oxidation.

On the left and the right sidewalls of the pillar 12 or 14 where thewall oxide layer 18 is formed, a spacer 40 is formed along an outersurface of the wall oxide layer 18. Also, the spacer 40 is formed toprotect the surface of the pillars 12 and 14 and may include a nitridefilm with a low etch selectivity.

In a semiconductor device according to an embodiment of the presentinvention, since the bit line 22 is not formed between the pillars 12and 14, but is formed inside the pillars 12 and 14, it is possible tosecure a broad space between the adjacent bit lines 22, therebyimproving a process margin of the bit line 22 and reducing parasiticcapacitance generated between the adjacent bit lines 22.

To further explain the advantages of the present invention, asillustrated by the embodiments described above, features of the presentinvention will be discussed further. According to an embodiment of thepresent invention, a first pillar 12 is formed to extend from asemiconductor substrate. First bit lines 22 are formed on at least twosidewalls of the first pillar 12. The first bit lines 22 include metalsilicide films, respectively. The first bit lines 22 are formed at firstand second sidewalls. The first sidewall may be opposite to the secondsidewall. The first bit lines 22 are formed by a rapid thermal annealingprocess.

A lower junction region 15 is formed at a lower portion of the firstpillar 12. The first bit lines 22 are coupled to the lower junctionregion 15.

Second bit lines 26 may be formed over the first bit lines 22,respectively. The second bit lines 26 are coupled to the first bit lines22, respectively. The second bit lines may include a titanium nitridefilm (TiN), a tungsten (W) film, a tungsten nitride film (WN), or acombination thereof.

A gate (the upper hatching region in FIG. 12) may be formed over a thirdsidewall of the first pillar 12. The gate is coupled to the first bitlines 22. An upper junction region 12 a is formed at an upper portion ofthe first pillar 12. The gate is coupled to the vertical channel region12 b.

In another embodiment of the present invention, a first pillar 12 isformed over a semiconductor substrate. At least two sidewalls of thefirst pillar 12 are transformed into conductive films to form first bitlines 22. The conductive films may be metal silicide films.

The step of transforming the sidewalls of the first pillar 12 intoconductive films may include (i) forming metal layers 24 over the twosidewalls of the first pillar 12, and (ii) performing a rapid thermalannealing process on the metal layers 24 to transform the two sidewallsof the first pillar 12 into the conductive films. Second bit lines 26are formed over the first bit lines 22, respectively, and are coupled tothe first bit lines 22.

The first pillar 12 has a lower junction region 12 b, and the first bitlines 22 are coupled to the lower junction region 12 b.

FIGS. 1-12 are cross-sectional diagrams illustrating a method forfabricating a semiconductor device according to an embodiment of thepresent invention.

Hereinafter, a method for forming a semiconductor device according to anembodiment of the present invention will be described in more detailwith reference to FIGS. 1-12.

Referring to FIG. 1, a semiconductor substrate 10 is patterned to formthe first pillar 12 and the second pillar 14. Although FIG. 1 shows across-sectional view, these pillars 12 and 14 may be formed with a linepattern extending along front and rear directions (forwards andbackwards) or may be formed with a structure extending vertically with apillar shape from the semiconductor substrate 10.

There are various methods for forming the pillars 12 and 14. As shown inFIG. 1, in an embodiment, a pillar hard mask 16 is formed over thesemiconductor substrate 10 and the semiconductor substrate 10 is etchedusing the pillar hard mask 16 as a mask to obtain the pillars 12 and 14.For the hard mask 16, various materials such as a photoresist film, anoxide film, a nitride film, a silicon oxide nitride film, or anamorphous carbon layer may be used with a different etch selectivityfrom the semiconductor substrate 10 including a silicon (Si) material.Although it is not shown, in an embodiment, a selective epitaxial growthprocess of the silicon over the semiconductor substrate 10 may be usedto obtain the pillars 12 and 14. After the pillars 12 and 14 are formed,an oxidation process is performed on the pillars 12 and 14 to form thewall oxide layer 18 on the surface of the pillars 12 and 14.

As shown in FIG. 2, an anisotropic etch process or a spacer etch processis performed to remove the wall oxide layer 18 disposed over thesemiconductor substrate 10 while maintaining the oxide layer 18 disposedover the sidewalls of the pillars 12 and 14. Also, by the anisotropicetch process, the semiconductor substrate 10 is further etched to agiven depth to expose a part of the semiconductor substrate 10, whichincludes silicon Si. The heights of the pillars 12 and 14 can beadjusted so that the lower portion of the pillars 12 and 14 that do notinclude the wall oxide layer 18 can be further formed later.

The lower junction region 15 is formed in a lower portion of the pillars12 and 14. There are various methods for forming the lower junctionregion 15. For example, an ion-implanting process or a plasma dopingprocess may be used. The plasma doping process may be performed withphosphorus (Ph) or arsenic (As). Meanwhile, as mentioned above, thelower junction region 15 may be formed as an N-type or P-type.

Referring to FIG. 3, a first conductive layer 24 is formed over thewhole surface of the pillars 12 and 14, including the lower junctionregion 15. The first conductive layer 24 includes a metal material.Specifically, in an embodiment, the first conductive layer 24 mayinclude cobalt (Co). The first conductive layer 24 is uniformly formedover the whole surface including the sidewalls of the pillars 12 and 14and may be deposited by a Chemical Vapor Deposition (CVD) process or anAtomic Layer Deposition (ALD) process.

As shown in FIG. 4, an anisotropic etch (or spacer etch) process isperformed to remove the first conductive layer 24 formed over thesemiconductor substrate 10. Although the first conductive layer 24disposed over top surfaces of the pillars 12 and 14 may be removedtogether, the first conductive layer 24 disposed at the sidewalls of thepillars 12 and 14 remains. During this process, the lower junctionregion 15 is separated into two. In addition, while the semiconductorsubstrate 10 disposed between the two pillars 12 and 14 is etched to agiven depth, the lower junction region 15 over the semiconductorsubstrate is removed while the lower junction region 15 disposed in thelower portions of the pillars 12 and 14 remains.

Referring to FIG. 5, a Rapid Thermal Annealing (RTA) process isperformed to form the first bit line 22 inside the pillars 12 and 14. Ifthe RTA process is performed, the metal material of the first conductivelayer 24 reacts with the silicon Si of the pillars 12 and 14 to form ametal silicide inside the pillars 12 and 14. If the metal material iscobalt (Co), the metal silicide formed is cobalt silicide (CoSi₂). Themetal silicide operates as a bit line in the semiconductor device, andis designated as the first bit line 22. After the RTA process, the firstconductive layer 24 that remains at the sidewalls of the pillars 12 and14. That is, the first conductive layer 24 that has not reacted with thesilicon (without forming a silicide) due to the wall oxide layer 18, isremoved by a cleaning process.

Although the first bit line 22 is formed on the left and the rightsidewalls of the pillars 12 and 14 as shown in FIG. 5, it may be formedon only one sidewall of the pillars 12 and 14. In this case, it isnecessary to form the first conductive layer 24 only on one sidewall ofthe pillars 12 and 14. For example, in FIG. 4, a slant etch process isperformed to remove the first conductive layer 24 formed on one sidewall(left side surface or right side surface) of the pillars 12 and 14.Thereafter, the RTA process shown in FIG. 4 is performed to form thefirst bit line 22 on only one sidewall of the pillars 12 and 14.

As shown in FIG. 6, a second conductive layer 28 is formed over thewhole surface of the pillars 12 and 14 including the first bit line 22.The second conductive layer 28 also includes a conductive material, suchas metal, and may include a titanium nitride film (TiN), a tungsten (W)film, a tungsten nitride film (WN), or a stacked structure including atleast two or more among a titanium nitride film (TiN), a tungsten (W)and a tungsten nitride film (WN). The second conductive layer 28 isuniformly formed over the whole surface including the sidewalls of thepillars 12 and 14 and may be deposited by a Chemical Vapor Deposition(CVD) process or an Atomic Layer Deposition (ALD) process.

Referring to FIG. 7, an anisotropic etch (spacer etch) process isperformed to remove the second conductive layer 28 formed over thesemiconductor substrate 10. The semiconductor substrate 10 may also beetched to a given depth so that the heights of the pillars 12 and 14 mayalso be relatively higher. As a result, the second conductive layer 28disposed on the surface of the two adjacent pillars 12 and 14 may beelectrically isolated from each other.

As shown in FIG. 8, a first interlayer insulating film 32 is depositedover the semiconductor substrate and fills in a space between thepillars 12 and 14. The first interlayer insulating film 32 is thenplanarized. The second conductive layers 28 formed at the sidewalls ofthe adjacent pillars 12 and 14 are thus insulated from each other. Thefirst interlayer insulating film 32 may include SiO₂, Boron PhosphorusSilicate Glass (BPSG), Phosphorus Silicate Glass (PSG), Tetra EthylOrtho Silicate (TEOS), Un-doped Silicate Glass (USG), Spin On Glass(SOG), High Density Plasma (HDP), Spin On Dielectric (SOD), PlasmaEnhanced Tetra Ethyl Ortho Silicate (PE-TEOS), or Silicon Rich Oxide(SROx).

Referring to FIG. 9, the first interlayer insulating film 32 ispartially removed. A top surface of the remaining first interlayerinsulating film 32 is level to or higher than an upper end of the firstbit line 22 or an upper end of the lower junction region 15.

As shown in FIG. 10, a portion of the second conductive layer 28 thatremains over the sidewalls of the pillars 12 and 14 is removed by acleaning process. As a result, the second conductive layer 28 thatremains is as high as the first interlayer insulating film 32. Theremaining second conductive layer 28 becomes the second bit line 26.Although the second bit line 26 is not located inside but outside of thepillars 12 and 14, the second bit line 26 is in contact with the firstbit line 22 to reduce resistance of the whole bit lines 22 and 26.

However, the process for forming the second bit line 26 shown in FIGS.6-10 is optional in an embodiment of the present invention. That is, theoperation of the semiconductor device according to an embodiment of thepresent invention may be performed with only the first bit line 22formed inside the pillars 12 and 14. The second bit line 26 can beadditionally formed outside the first bit line in order to furtherreduce resistance of the first bit line 22.

Referring to FIG. 11, a spacer material is deposited over the wholesurface of the pillars 12 and 14 where the second conductive layer hasbeen 28 removed. An etch-back process is performed to form a spacer 40only at the sidewalls of the pillars 12 and 14. For this spacermaterial, a nitride film may be used. The spacer 40 serves as aprotector to protect the surface of the pillars 12 and 14 along with thepillar hard mask 16.

As shown in FIG. 12, a second interlayer insulating film 34 is formedover the whole surface of the pillars 12 and 14 and the spacer 40 tolevel the whole structure including the pillars 12 and 14.

Although it is not shown in the drawing, a channel ion-implanting and anupper junction region ion-implanting process are performed on thepillars 12 and 14 to form a gate (the upper hatching region) in contactwith the vertical channel regions 12 b and 14 b in the correspondingregion to the vertical channel regions 12 b and 14 b. In a plan view,the gate is extended in a vertical direction to the bit lines 22 and 26and may be formed to surround the pillars 12 and 14 or the gate may beformed as a double gate in contact with both sidewalls of the pillar 12or 14. Thereafter, the pillar hard mask 16 disposed over the pillar 12or 14 is removed to form a capacitor connected with the upper junctionregions 12 a and 14 a.

The above-described method for fabricating a semiconductor deviceaccording to an embodiment of the present invention may easily form thebit line 22 inside the pillar 12 or 14 and secure a broad space betweenneighboring bit lines 22 coupled to the adjacent pillars 12 and 14,respectively. Thus, the process margin can increase and parasiticcapacitance between neighboring bit lines 22 can be reduced.

The memory device according to an embodiment of the present inventionmay be applied to dynamic random access memories (DRAMs), but it is notlimited thereto and it may be applied to static random access memories(SRAMs), flash memories, ferroelectric random access memories (FeRAMs),magnetic random access memories (MRAMs), or phase change random accessmemories (PRAMs).

The above-described memory device according to an embodiment of thepresent invention can be used, for example, in desktop computers,portable computers, computing memories used in servers, graphicsmemories having various specs, and mobile electronic devices astechnology continues to evolve. Further, the above-describedsemiconductor device may be provided to various digital applicationssuch as mobile recording mediums including a memory stick, multimediacard (MMC), secure digital (SD), compact flash (CF), extreme digital(xD) picture card, and a universal serial bus (USB) flash device as wellas various applications such as MP3P, portable multimedia player (PMP),a digital camera, a camcorder, and a mobile phone. A semiconductordevice may be applied to a technology such as multi-chip package (MCP),disk on chip (DOC), or embedded device. The semiconductor device may beapplied to a CMOS image sensor to be provided to various fields such asa camera phone, a web camera, and a small-size image capture device formedicine.

As described above, a semiconductor device and a method for fabricatingthe same according to an embodiment of the present invention may enablethe bit line to be formed easily, increase the bit line process marginand reduce capacitance between the adjacent bit lines.

The above embodiments of the present invention are illustrative and notlimitative. Various alternatives and equivalents are possible. Theinvention is not limited by the embodiments described herein. Nor is theinvention limited to any specific type of semiconductor device. Otheradditions, subtractions, or modifications are obvious in view of thepresent disclosure and are intended to fall within the scope of theappended claims.

What is claimed is:
 1. A semiconductor device, comprising: a firstpillar and a second pillar each including a vertical channel region; afirst bit line located inside a lower portion of any of the first pillarand the second pillar; a second bit line located outside any of thefirst and second pillars, and being in contact with the first bit line;and an interlayer insulating film located between the first pillar andthe second pillar, wherein the first and second pillars are protrudingregions of a semiconductor substrate.
 2. The semiconductor deviceaccording to claim 1, wherein the first bit line includes a metalsilicide.
 3. The semiconductor device according to claim 2, wherein themetal silicide includes a cobalt silicide (CoSi₂).
 4. The semiconductordevice according to claim 1, wherein the first bit line is disposed at afirst sidewall and a second sidewall of any of the first pillar and thesecond pillar.
 5. The semiconductor device according to claim 1, whereinthe second bit line includes a titanium nitride film (TiN), a tungsten(W) film, a tungsten nitride film (WN) or a combination thereof.
 6. Thesemiconductor device according to claim 1, wherein the second bit lineis disposed outside a first sidewall and a second sidewall of any of thefirst pillar and the second pillar.
 7. The semiconductor deviceaccording to claim 1, the device further comprising: an upper junctionregion located in an upper portion of any of the first pillar and thesecond pillar; and a lower junction region located below the verticalchannel region of any of the first pillar and the second pillar.
 8. Thesemiconductor device according to claim 7, wherein the first bit line islocated inside the lower junction region.
 9. The semiconductor deviceaccording to claim 1, the device further comprising a wall oxide layerlocated over a surface of any of the first pillar and the second pillar.10. The semiconductor device according to claim 9, wherein the walloxide layer is located over a surface of a sidewall of the verticalchannel region of any of the first pillar and the second pillar andextends over a surface of a sidewall of the upper junction region. 11.The semiconductor device according to claim 1, the device furthercomprising a spacer located over a sidewall of any of the first pillarand the second pillar.
 12. The semiconductor device according to claim11, wherein the spacer includes a nitride film.
 13. The semiconductordevice according to claim 7, wherein the upper junction region and thelower junction region are N-type regions and the vertical channel regionis a P-type region.
 14. The semiconductor device according to claim 7,wherein the upper junction region and the lower junction region areP-type regions and the vertical channel region is an N-type region. 15.The semiconductor device according to claim 1, the device furthercomprising a nitride film located over any of the upper portion of thefirst pillar and the second pillar.
 16. The semiconductor deviceaccording to claim 1, wherein the interlayer insulating film includes: afirst interlayer insulating film; and a second interlayer insulatingfilm located over an upper portion of the first interlayer insulatingfilm.
 17. The semiconductor device according to claim 1, wherein thefirst pillar and the second pillar include line patterns, respectively.18. The semiconductor device according to claim 1, the device furthercomprising a gate located in a region corresponding to the verticalchannel region and in contact with the vertical channel region.
 19. Thesemiconductor device according to claim 7, the device further comprisinga capacitor coupled to the upper junction region of any of the firstpillar and the second pillar.
 20. The semiconductor device according toclaim 1, wherein the interlayer insulating film contacts an outersidewall of the second bit line.